This invention relates to a semiconductor device, and in particular to a semiconductor device having a silicon-on-insulator (SOI) structure.
A SOI structure typically is constituted by a first and second silicon layers separated by a silicon oxide layer. In a first form of SOI structure, a single crystal silicon film is formed on a silicon substrate on whose surface is deposited an insulating film of silicon oxide. In a second form of structure, a silicon oxide film is formed at a small depth from the surface of a single crystal silicon substrate. In a third form of SOI structure, a single crystal silicon plate is thermocompression bonded to a substrate which has a silicon oxide film on its surface.
The main advantage of SOI technology is that it has a reduced power consumption when compared with known technologies. One trend in VLSI microelectronics over the last few years has been the incorporation of integrated circuits with ever greater complexity and ever greater power consumption. Increased power consumption can impose serious limitations on the use of integrated circuits, for example, portable applications. Even though the trend in recent years has been to use low power complementary metal oxide silicon (CMOS) technology on bulk silicon combined with power management techniques, power consumption remains an issue. SOI technology offers a further reduction in power consumption, and for this reason is an attractive technology for future mainstream VLSI products. In RF applications, particularly mobile communications, bipolar technology is prevalent because of its ability to operate at high frequencies. In these applications, power consumption can be relatively high. Again, SOI technology offers a reduction in power consumption and for this reason is an attractive technology for future mobile communication products. SOI technology offers improvements in junction area, leakage, isolation and capacitance, and leads to reduced power consumption when compared to bulk devices.
Unfortunately, SOI technology is not without drawbacks. Thus, the presence of a buried oxide reduces thermal conductivity to the substrate. Consequently, heat dissipation is reduced, and this can limit the operating performance of the device concerned, particularly in applications where current handling is important.
Where SOI technology is used in VLSI products, each of the semiconducting devices forming such a product requires isolation. A common form of isolation, in both bulk and SOI technology, is that of trench isolation. In SOI technology, the combination of trench isolation and the buried oxide results in electrically isolated xe2x80x9ctubsxe2x80x9d in which the active devices are formed. For good electrical isolation, the trench depth must equal the upper layer thickness, i.e. the trench must reach the buried oxide. Failure to do so would result in a leakage path between tubs. A typical layer thickness above the buried oxide is 2-3 xcexcm, and the trench needed is regarded as xe2x80x9cshallowxe2x80x9d.
FIG. 1 shows a typical form of isolation for SOI technology. FIG. 1 shows a part of a VLSI SOI device, the device being constituted by a silicon substrate 1, a silicon oxide (buried oxide) layer 2 and a surface layer of silicon 3. A plurality of trenches 4 (only two of which are shown) are formed in the device, each trench being constituted by a dielectric liner 4a and a polysilicon in-fill 4b. Each pair of adjacent trenches 4 defines a tub 3a in the surface layer 3 of silicon. A semiconductor device (not shown) can then be formed in each of the tubs 3a. 
The trenches 4 provide good electrical isolation for each of the tubs 3a. Unfortunately, the good electrical isolation of the tubs 3a is accompanied by good thermal isolation; and, as mentioned above, this leads to a reduction in heat dissipation, and possibly a limiting of the operating performance of the devices concerned. This problem is particularly important in bipolar and bipolar CMOS technologies, but the problem can also arise with high density CMOS devices.
In an attempt to reduce thermal isolation, the inclusion of thermally-conducting pillars directly to contact the substrate is expected to improve heat dissipation. Similarly, extending trenches just into the substrate layer, and to remove the base portions of the dielectric liners so that the trench in-fill material contacts the substrate layer, is expected to improve heat dissipation. However, there are several disadvantages with both these approaches. In the first case, there is the need to introduce extra processing to produce the pillar, and to incorporate the pillar in such a way so that it does not electrically connect the device with the substrate. In the second case, there is the need to introduce extra processing to remove only specific parts of the dielectric liner material without damaging the remaining liner. Both necessitate increased processing time, more complex processing and higher costs.
The present invention provides a semiconductor device comprising a substrate having an insulating layer formed on a surface thereof, a semiconductor material layer located on a surface of the insulating layer, a trench that extends from a surface of the semiconductor material layer through the insulating layer and into the substrate, an insulating liner located on the side walls and the base of the trench, and an in-fill of thermally-conductive material within the insulating liner, wherein the insulating liner, the in-fill material and the distance over which the trench extends into the substrate are such as to promote flow of heat from the semiconductor material layer to the substrate, the insulating liner completely surrounding the in-fill material at least where the trench extends into the substrate, and said distance is at least 1 xcexcm.
Advantageously, said distance lies within the range of from 1 xcexcm to 5 xcexcm, and preferably within the range of from 3 xcexcm to 5 xcexcm.
In a preferred embodiment, there are two trenches, each of which has the features defined above, and wherein an active device is formed in the semiconductor material layer between the two trenches. More preferably, there are a plurality of trenches, each of which has the features defined above, and wherein a respective active device is formed in the semiconductor material layer between each pair of adjacent trenches.
Preferably, the semiconductor material layer is a silicon layer, more preferably a silicon layer of single crystal formation.
Advantageously, the substrate is a silicon substrate, and the insulating layer is a silicon oxide layer.
Preferably, the or each liner is constituted by an outer layer of silicon oxide and an inner layer of silicon nitride, and the or each outer silicon oxide layer has a thickness of substantially 1,000 xc3x85xc2x0, and the or each inner silicon nitride layer has a thickness of substantially 300 xc3x85xc2x0.
Conveniently, the in-fill material is polysilicon, and the width of the or each trench is substantially 0.8 xcexcm.
Preferably, the thickness of the or each liner is at least an order of magnitude less than the thickness of the insulating layer.